Published March 2000

ANALOG PLD ANYONE?

by Tom Cantrell

Start • Viva la Differential • Virtual Prototype • Sources and PDF

VIRTUAL PROTOTYPE

The amplifiers and such aren’t conceptually different from the discrete units of yore. Rather, the virtues of the PAC become most apparent when it comes time for wiring something up. PAC-Designer software makes it a point-and-click rather than ponder-and-curse affair.

The price is definitely right. You can download 30-day, try-before-you-buy software for free from the Lattice web site, and the cost for an entire kit (see Photo 1), including the software (an EV-board, download cable, etc.), is only $149.

Photo 1—Is the PAC right for you? At only $149 for a complete evaluation kit, it doesn’t cost much to give it a whirl.

The limited complexity and purposeful nature of the part make for a tool with a short learning curve and fast turnaround. Worst case senario, you’re looking at connecting a few lines, choosing a few gain settings and capacitor values, and so on.

In fact, for a typical filter and such, it’s even easier than that. Browse the library of canned functions or take advantage of built-in macro generators (see Photo 2). It takes just a minute or two to fire up PAC-Designer, point and click on a design, and blast it into silicon using a JTAG adapter cable connected to your PC parallel port.

	Photo 2—Put away your op-amp cookbook and solder iron. With the Lattice PAC-Designer software, pre-defined and macro-generated filters, and the like are a mouse click away.

If you want to test drive your design on the screen, a built-in simulator does the trick (see Photo 3). Once again, the fact that there aren’t many circuits, pins, and so on to deal with makes simulation simple and fast. However, programming the EEPROM configuration takes about 100 ms, so it’s almost easier to simply blow and go. Just try it—you’ve got 10k (EEPROM write endurance) chances to get it right.

(Click here for photo)

Photo 3—Test driving a design, in this case a combination low-pass (red) and band-pass (green) filter, is easy using PAC-Designer’s built-in simulator.

Unlike fancy FPGAs, which keep their internal organization a deep, dark secret, PAC-Designer bares all, supporting a variety of file formats, including text (.txt), JEDEC hex file (.jed), and JTAG Serial Vector Format (.svf), that allow programming a PAC along with the rest of the devices in a JTAG chain.

Note that the PAC version of JTAG doesn’t support boundary scan (i.e., reading/writing pins)—something that would be neat but simply isn’t feasible for a non-digital chip, because it would require a DAC for every output and an ADC for every input. Rather, JTAG is used for programming the PAC configuration and as a conduit for connection with other chips in a JTAG chain.

DÉJÀ VU!

I think the Lattice chips are neat, but I must admit to being a little gun-shy about making rosy predictions. The fact is, the PAC is strikingly similar to a chip I sang the praises of back in 1995, the EPAC from IMP Inc. ("EPAC Epoch," Circuit Cellar 58).

You say you’ve never heard of the EPAC? I suspect you’re not alone. And, if you head over to www.imp.com, you’ll see some handy chips but no EPACs. It turns out that shortly after the EPAC’s introduction, IMP encountered some turbulence in their operation. That’s a polite way to describe management shakeup, irate creditors, and a 10:1 reverse stock split!

At the time, I also raised a red flag about the $20 (1k) asking price. Yeah, point-and-click analog chips are neat, but that was clearly pushing it. And, although I think IMP gave it the good old college try, it just seemed they had trouble making the transition beyond their analog foundry roots into the hurly-burly of the merchant market.

It’s tempting to say that the EPAC was an isolated case of bad timing rather than a bad idea, but then how do you explain the Motorola MPAA programmable analog array I wrote about in ’97 ("A(r)Ray of Analog Hope," Circuit Cellar 87)? It’s dead and gone, too. Once again, there are extenuating circumstances. To wit, the MPAA went down with the ship when Motorola threw in the towel and bagged their entire programmable logic effort.

In its favor, the PAC price (less than $7 in thousands) seems reasonable, and the tools (PAC-Designer, EV-board, etc.) are a good deal, too. Second, Lattice seems to be doing well and, unless there’s some skeleton lurking in a closet, doesn’t appear a likely candidate for financial flameout. Furthermore, Lattice knows a lot more about selling programmable logic than IMP or Motorola ever did.

On the other hand, I think there’s a bit of a challenge involved in reaching and convincing traditional analog electronics types. The DSP proves such crossover is possible. But, look at who’s successful in the DSP biz—TI, Analog Devices, Motorola—all companies notable for long-standing and big ongoing business selling non-digital chips. I think the concept of an analog PLD is a winner, but the Lattice sales force is going to have to knock on some new doors and try to cut in line in front of some heavyweights.

So, is the third time the charm, or is it three strikes, you’re out? Will the PAC succeed in bridging the analog gap? Or, will it be yet another example of "tomorrow’s technology of tomorrow" like the EPAC and MPAA?

I don’t know for sure, but I’ve got a feeling it’s only a matter of time before the 1s and 0s manage to get this one step (albeit a big one) closer.

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