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December 2006, Issue 197

Ethernet on a Chip


by Fred Eady


Start Ethernet SoC I've Been Had! AX110xx Development Kit Keil's Been Had 2! Ethernet Module Serious Stuff Sources and PDF

I’VE BEEN HAD!

From what I’ve seen thus far, the AX11005 is a pretty heavy little microcontroller. It would be close to impossible to attempt to apply an application to the AX11005 hardware without a good debugging system. The AX11005 doesn’t disappoint. It comes standard with an on-chip in-circuit emulator feature that’s designed to interface with a piece of external ICE hardware. The task assigned to the ICE is to manage communications between the AX11005’s on-chip ICE circuitry and a software debugger application running on a PC. The external ICE hardware that mates with the AX11005’s on-chip ICE circuitry is called the Hardware Assisted Debugger (HAD). The latest version of HAD is called HAD2. As you can see in Photo 1, I’ve been HAD.

(Click here to enlarge)

Photo 1—The HAD2 is powered by the USB port and manages communications between the AX11005 on-chip ICE circuitry and the debugging application running on a companion PC.

Powered by the USB port, the HAD2 uses USB Full Speed technology to interface the AX11005’s internal debugging system to the debugging application running behind the USB interface on a PC. My HAD2 hardware is from Digital Core Design, which also supplied the Windows-based debugging application software. The HAD2 and Windows debugging software come bundled together. The HAD2 debugging software package is fully compatible with all existing 8051/80390 C compilers and assemblers. In addition to debug duty, the debugging software can be used as a software simulator too.

The HAD2 package was originally designed for SoC designers that needed the capability of debugging applications before they were to be committed to silicon. It’s pretty obvious now that the AX11005 contains a Digital Core Design (DCD) 8051/80390 IP Core, because the AX11005’s DCD IP Core is specifically designed to work with the HAD2 and the DCD Debug IP Core. This mix of IP cores and the HAD2 is called DCD on Chip Debug System (DoCD).

The Debug IP Core is a real-time hardware debugger that enables a full nonintrusive view of the on-chip registers, memories, and peripherals associated with the DCD IP Core, which is the 8051/80390 IP core in this case. The DoCD debugging system doesn’t require any resources from the target. Thus, all of the target device’s features and peripherals can be accessed during the debug phase. As you’ve already ascertained, the DoCD system is complete and needs nothing else in the way of features to make it better. But it does get better. You can also use the DoCD system to program the target device’s program flash memory.