February
1998, Issue 91
Codesign
The
Evolving Relationship Between Hardware and Software
The integration
levels and performance provided by today’s FPGA
vendors, plus the maturity of tools available for mapping
the register-transistor-level description of hardware,
enable hardware emulation of a target system to be realized
fairly quickly and easily.
The advantage
of the hardware-emulation approach, led by systems such
as Quickturn Design Systems’ System Realizer, is
that they provide gate-for-gate, wire-for-wire prototyping
of the target system. In some cases, they may even be
able to operate at the target system’s full operating
speed.
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Figure
1—Chip manufactures are doing
an excellent job of emulating the logic that
goes onto a chip, as evidenced by shrinking
debugger ports on new, complex chips. Next
tasks: emulating the chip in both systems
and standalone environments as well as wliminating
bugs.
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Motorola used
System Realizer during the verification phase of the
MC68060 and ColdFire microprocessor cores (see Figure
1). During the ’060 verification, prior to first
silicon, over one trillion instructions were run to
verify that the chip was running instructions correctly,
as illustrated in Figure 2.
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Figure
2—The 68060 verification experience
demonstrated that the verification process
weeds out many bugs that would have slipped
by through the sheer number of instructions
run against the part. However, a certain number
of bugs only manifest themselves in a full-blown
end system that includes memory components,
peripherals, and perhaps other processors.
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The main downside
to the hardware-emulation-only approach is the investment
in front-end work required to map the system into programmable
logic, although tools designed solely for this task
greatly facilitate the process. Once the system is mapped,
hardware changes can be quickly and easily implemented.
This step,
however, must be completed at some stage of the design
process anyway, to analyze the validity of the customer-designed
logic. The only disadvantage is that the gate-level
implementation must be completed at an earlier stage
in the project.
