2nd
Place




FPGA WINNERS ANNOUNCEMENT

2nd Place

Vitit Kantabutra

Contest Entry # DL205: Better Adders for the AT40K FPGAs

Abstract. Adder speed and size are undeniably crucial factors in determining the success of a family of FPGAs. I will present fast, small adders for the AT40K FPGA family.

These adders are simple carry-skip adders specifically designed for FPGAs, where cells and interconnects are optimized for ripple chains. Our adders make good use of these optimized ripple chains instead of trying to outperform them. Yet I composed ripple chains in such a way that shortens the critical path delay significantly without too much cost.

As an example I have completely designed a 16-bit adder and a 32-bit adder. Our 16-bit adder is approximately 23.5% faster than its ripple counterpart, and is 37% larger. The 32-bit adder, on the other hand, is 34% faster than its ripple counterpart, while using only 28% more cells. On the contrary, a 16-bit carry-select adder automatically generated by Atmel's IDS is more than 3 times as large as the ripple adder, and sometimes operates more slowly than ripple adders in practice.

Unlike the IDS’s carry-select adders, our carry-skip adders don’t duplicate ripple chains for any bit position. Instead, our adders divide the adder’s bit positions into groups, and determines inexpensively whether the carry into a group will be propagated through to as carry out of that group. If so, that group is said to be "skipped." The carry out of a skipped group of bits can be determined with a multiplexer without having to wait for the carry in to ripple slowly through the bit positions of that group.


(Click to Enlarge)

In our 16-bit adder, the 16 bit positions are divided into 3 blocks of sizes 5, 6, and 5. Our 32-bit adder is divided up into blocks of sizes 10, 12, and 10. In both adders, the most and least significant blocks are just ordinary ripple adder blocks, but the middle block is a special block with a skip mechanism. No carry signal ripples slowly all the way through from lsb to msb, making the worst-case delay much better than that of the ripple adder.

End of Abstract

 

 

 
     
 
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